3x4_res_ladder_diag.sch 4.1 KB

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  1. v 20130925 2
  2. C 48200 43100 1 270 1 resistor-1.sym
  3. {
  4. T 48600 43400 5 10 0 0 90 2 1
  5. device=RESISTOR
  6. T 48200 43100 5 10 0 1 0 6 1
  7. footprint=0805
  8. T 48100 43200 5 10 0 1 180 2 1
  9. refdes=R110
  10. T 48100 43500 5 10 1 1 0 6 1
  11. value=100k
  12. }
  13. N 46300 45000 46300 49000 4
  14. N 43500 45000 43500 48500 4
  15. N 44300 47200 48300 47200 4
  16. N 44300 46200 48300 46200 4
  17. N 44300 45200 48300 45200 4
  18. N 44300 44200 50000 44200 4
  19. {
  20. T 50100 44300 5 10 1 1 0 0 1
  21. value=A/D input
  22. }
  23. N 48300 44200 48300 44000 4
  24. N 44900 45000 44900 48500 4
  25. N 48300 43100 48300 42800 4
  26. C 49100 42900 1 90 0 capacitor-1.sym
  27. {
  28. T 48400 43100 5 10 0 0 90 0 1
  29. device=CAPACITOR
  30. T 48200 43100 5 10 0 0 90 0 1
  31. symversion=0.1
  32. T 49100 42900 5 10 0 1 0 0 1
  33. footprint=0805
  34. T 49000 43500 5 10 1 1 0 0 1
  35. value=1n
  36. }
  37. C 46100 49000 1 0 0 3.3V-plus-1.sym
  38. B 46800 48400 1200 400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
  39. N 48900 43800 48900 44200 4
  40. T 47100 48500 9 10 1 0 0 0 1
  41. buttons
  42. N 48900 42900 48300 42900 4
  43. C 48400 46200 1 90 0 resistor-1.sym
  44. {
  45. T 48000 46500 5 10 0 0 90 0 1
  46. device=RESISTOR
  47. T 48100 46400 5 10 1 1 90 0 1
  48. refdes=10k
  49. }
  50. C 48400 45200 1 90 0 resistor-1.sym
  51. {
  52. T 48000 45500 5 10 0 0 90 0 1
  53. device=RESISTOR
  54. T 48100 45500 5 10 1 1 90 0 1
  55. refdes=10k
  56. }
  57. C 48400 44200 1 90 0 resistor-1.sym
  58. {
  59. T 48000 44500 5 10 0 0 90 0 1
  60. device=RESISTOR
  61. T 48100 44400 5 10 1 1 90 0 1
  62. refdes=10k
  63. }
  64. C 43800 48400 1 0 0 resistor-1.sym
  65. {
  66. T 44100 48800 5 10 0 0 0 0 1
  67. device=RESISTOR
  68. T 44100 48700 5 10 1 1 0 0 1
  69. refdes=3k3
  70. }
  71. C 45100 48400 1 0 0 resistor-1.sym
  72. {
  73. T 45400 48800 5 10 0 0 0 0 1
  74. device=RESISTOR
  75. T 45300 48700 5 10 1 1 0 0 1
  76. refdes=3k3
  77. }
  78. N 45100 48500 44700 48500 4
  79. N 46000 48500 46300 48500 4
  80. N 43500 48500 43800 48500 4
  81. C 48200 42500 1 0 0 gnd-2.sym
  82. T 41700 44700 9 24 1 0 0 0 7
  83. 1 2 3
  84. 4 5 6
  85. 7 8 9
  86. * 0 #
  87. C 43300 48000 1 270 0 switch-diag.sym
  88. {
  89. T 43700 47900 5 10 0 0 270 0 1
  90. device=SWITCAP-switch
  91. T 43300 47700 5 10 0 1 270 0 1
  92. clock=clk
  93. T 43900 47800 5 10 1 1 0 0 1
  94. refdes=S1
  95. }
  96. C 44700 48000 1 270 0 switch-diag.sym
  97. {
  98. T 45100 47900 5 10 0 0 270 0 1
  99. device=SWITCAP-switch
  100. T 44700 47700 5 10 0 1 270 0 1
  101. clock=clk
  102. T 45300 47800 5 10 1 1 0 0 1
  103. netname=S2
  104. }
  105. C 46100 48000 1 270 0 switch-diag.sym
  106. {
  107. T 46500 47900 5 10 0 0 270 0 1
  108. device=SWITCAP-switch
  109. T 46100 47700 5 10 0 1 270 0 1
  110. clock=clk
  111. T 46700 47800 5 10 1 1 0 0 1
  112. netname=S3
  113. }
  114. C 43300 47000 1 270 0 switch-diag.sym
  115. {
  116. T 43700 46900 5 10 0 0 270 0 1
  117. device=SWITCAP-switch
  118. T 43300 46700 5 10 0 1 270 0 1
  119. clock=clk
  120. T 43900 46800 5 10 1 1 0 0 1
  121. refdes=S4
  122. }
  123. C 44700 47000 1 270 0 switch-diag.sym
  124. {
  125. T 45100 46900 5 10 0 0 270 0 1
  126. device=SWITCAP-switch
  127. T 44700 46700 5 10 0 1 270 0 1
  128. clock=clk
  129. T 45300 46800 5 10 1 1 0 0 1
  130. netname=S5
  131. }
  132. C 46100 47000 1 270 0 switch-diag.sym
  133. {
  134. T 46500 46900 5 10 0 0 270 0 1
  135. device=SWITCAP-switch
  136. T 46100 46700 5 10 0 1 270 0 1
  137. clock=clk
  138. T 46700 46800 5 10 1 1 0 0 1
  139. netname=S6
  140. }
  141. C 43300 46000 1 270 0 switch-diag.sym
  142. {
  143. T 43700 45900 5 10 0 0 270 0 1
  144. device=SWITCAP-switch
  145. T 43300 45700 5 10 0 1 270 0 1
  146. clock=clk
  147. T 43900 45800 5 10 1 1 0 0 1
  148. refdes=S7
  149. }
  150. C 44700 46000 1 270 0 switch-diag.sym
  151. {
  152. T 45100 45900 5 10 0 0 270 0 1
  153. device=SWITCAP-switch
  154. T 44700 45700 5 10 0 1 270 0 1
  155. clock=clk
  156. T 45300 45800 5 10 1 1 0 0 1
  157. netname=S8
  158. }
  159. C 46100 46000 1 270 0 switch-diag.sym
  160. {
  161. T 46500 45900 5 10 0 0 270 0 1
  162. device=SWITCAP-switch
  163. T 46100 45700 5 10 0 1 270 0 1
  164. clock=clk
  165. T 46700 45800 5 10 1 1 0 0 1
  166. netname=S9
  167. }
  168. C 43300 45000 1 270 0 switch-diag.sym
  169. {
  170. T 43700 44900 5 10 0 0 270 0 1
  171. device=SWITCAP-switch
  172. T 43300 44700 5 10 0 1 270 0 1
  173. clock=clk
  174. T 43900 44800 5 10 1 1 0 0 1
  175. refdes=S*
  176. }
  177. C 44700 45000 1 270 0 switch-diag.sym
  178. {
  179. T 45100 44900 5 10 0 0 270 0 1
  180. device=SWITCAP-switch
  181. T 44700 44700 5 10 0 1 270 0 1
  182. clock=clk
  183. T 45300 44800 5 10 1 1 0 0 1
  184. netname=S0
  185. }
  186. C 46100 45000 1 270 0 switch-diag.sym
  187. {
  188. T 46500 44900 5 10 0 0 270 0 1
  189. device=SWITCAP-switch
  190. T 46100 44700 5 10 0 1 270 0 1
  191. clock=clk
  192. T 46700 44800 5 10 1 1 0 0 1
  193. netname=S#
  194. }
  195. N 48300 45200 48300 45100 4
  196. N 48300 46200 48300 46100 4
  197. N 48300 47100 48300 47200 4
  198. L 51200 48500 50000 48500 3 0 0 0 -1 -1
  199. L 50000 48500 50000 42700 3 0 0 0 -1 -1
  200. L 50000 42700 51200 42700 3 0 0 0 -1 -1
  201. T 50500 45700 9 10 1 0 0 0 1
  202. uP
  203. L 49900 44300 50000 44200 3 0 0 0 -1 -1
  204. L 50000 44200 49900 44100 3 0 0 0 -1 -1