/** * * File Name : stm32f030.h * Author : Pat Beirne * Version : 12.0 * Date : 01/08/2014 * Copyright : 2014 Pat Beirne * License : GPL v3 * */ #ifndef __STM32F030_H #define __STM32F030_H /******************************************************************************/ /* Data Types Needed */ /******************************************************************************/ typedef signed long s32; typedef signed short s16; typedef signed char s8; typedef signed long const sc32; /* Read Only */ typedef signed short const sc16; /* Read Only */ typedef signed char const sc8; /* Read Only */ typedef volatile signed long vs32; typedef volatile signed short vs16; typedef volatile signed char vs8; typedef volatile signed long const vsc32; /* Read Only */ typedef volatile signed short const vsc16; /* Read Only */ typedef volatile signed char const vsc8; /* Read Only */ typedef unsigned long u32; typedef unsigned short u16; typedef unsigned char u8; typedef unsigned long const uc32; /* Read Only */ typedef unsigned short const uc16; /* Read Only */ typedef unsigned char const uc8; /* Read Only */ typedef volatile unsigned long vu32; typedef volatile unsigned short vu16; typedef volatile unsigned char vu8; typedef volatile unsigned long const vuc32; /* Read Only */ typedef volatile unsigned short const vuc16; /* Read Only */ typedef volatile unsigned char const vuc8; /* Read Only */ /******************************************************************************/ /* Peripheral registers structures */ /******************************************************************************/ /*------------------------ Analog to Digital Converter -----------------------*/ typedef struct { vu32 ISR; //0 vu32 IER; vu32 CR; vu32 CFGR1; vu32 CFGR2; //0x10 vu32 SMPR; vu32 RESERVED0; vu32 RESERVED1; vu32 TR; //0x20 vu32 RESERVED2; vu32 CHSELR; vu32 RESERVED4[5]; vu32 DR; //0x40 vu32 CCR; } ADC_TypeDef; /*------------------------ DMA Controller ------------------------------------*/ typedef struct { vu32 CCR; vu32 CNDTR; vu32 CPAR; vu32 CMAR; } DMA_Channel_TypeDef; typedef struct { vu32 ISR; vu32 IFCR; } DMA_TypeDef; /*------------------------ External Interrupt/Event Controller ---------------*/ typedef struct { vu32 IMR; vu32 EMR; vu32 RTSR; vu32 FTSR; vu32 SWIER; vu32 PR; } EXTI_TypeDef; /*------------------------ FLASH and Option Bytes Registers ------------------*/ typedef struct { vu32 ACR; vu32 KEYR; vu32 OPTKEYR; vu32 SR; vu32 CR; vu32 AR; vu32 RESERVED; vu32 OBR; vu32 WRPR; } FLASH_TypeDef; typedef struct { vu16 RDP; vu16 USER; vu16 Data0; vu16 Data1; vu16 WRP0; vu16 WRP1; } OB_TypeDef; /*------------------------ General Purpose and Alternate Function IO ---------*/ typedef struct { vu32 MODER; vu32 OTYPER; vu32 OSPEEDR; vu32 PUPDR; vu32 IDR; vu32 ODR; vu32 BSRR; vu32 LCKR; vu32 AFRL; vu32 AFRH; vu32 BRR; } GPIO_TypeDef; /*------------------------ Inter-integrated Circuit Interface ----------------*/ typedef struct { vu32 CR1; vu32 CR2; vu16 OAR1; u16 RESERVED2; vu16 OAR2; u16 RESERVED3; vu32 TIMINGR; // 0x10 vu32 TIMEOUTR; vu32 ISR; vu32 ICR; vu8 PECR; // 0x20 vu8 RESERVED4[3]; vu8 RXDR; vu8 RESERVED5[3]; vu8 TXDR; vu8 RESERVED6[3]; } I2C_TypeDef; /*------------------------ Independent WATCHDOG ------------------------------*/ typedef struct { vu32 KR; vu32 PR; vu32 RLR; vu32 SR; vu32 WINR; } IWDG_TypeDef; /*------------------------ Nested Vectored Interrupt Controller --------------*/ typedef struct { vu32 ISER[2]; u32 RESERVED0[30]; vu32 ICER[2]; u32 RSERVED1[30]; vu32 ISPR[2]; u32 RESERVED2[30]; vu32 ICPR[2]; u32 RESERVED3[30]; vu32 IABR[2]; u32 RESERVED4[62]; vu32 IPR[11]; } NVIC_TypeDef; typedef struct { vuc32 CPUID; vu32 ICSR; vu32 VTOR; vu32 AIRCR; vu32 SCR; vu32 CCR; vu32 SHPR[3]; vu32 SHCSR; vu32 CFSR; vu32 HFSR; vu32 DFSR; vu32 MMFAR; vu32 BFAR; vu32 AFSR; } SCB_TypeDef; /*------------------------ Power Control -------------------------------------*/ typedef struct { vu32 CR; vu32 CSR; } PWR_TypeDef; /*------------------------ Reset and Clock Control ---------------------------*/ typedef struct { vu32 CR; vu32 CFGR; vu32 CIR; vu32 APB2RSTR; vu32 APB1RSTR; // 0x10 vu32 AHBENR; vu32 APB2ENR; vu32 APB1ENR; vu32 BDCR; // 0x20 vu32 CSR; vu32 AHBRSTR; vu32 CRGR2; vu32 CFGR3; // 0x30 vu32 CR2; } RCC_TypeDef; /*------------------------ Real-Time Clock -----------------------------------*/ typedef struct { vu32 TR; vu32 DR; vu32 CR; vu32 ISR; vu32 PRER; // 0x10 u32 RESERVED0[2]; vu32 ALRMAR; u32 RESERVED1; // 0x20 vu32 WPR; vu32 SSR; vu32 SHIFTR; vu32 TSTR; // 0x30 vu32 TSDR; vu32 TSSSR; vu32 CALR; vu32 TAFCR; // 0x40 vu32 ALRMASSR; } RTC_TypeDef; /*------------------------ Serial Peripheral Interface -----------------------*/ typedef struct { vu16 CR1; u16 RESERVED0; vu16 CR2; u16 RESERVED1; vu16 SR; u16 RESERVED2; vu16 DR; u16 RESERVED3; vu16 CRCPR; u16 RESERVED4; vu16 RXCRCR; u16 RESERVED5; vu16 TXCRCR; u16 RESERVED6; } SPI_TypeDef; /*------------------------ SysCfg --------------------------------------------*/ typedef struct { vu32 CFGR1; vu32 reserved; vu32 EXTICR[4]; vu32 CFGR2; } SYSCFG_TypeDef; /*------------------------ SystemTick ----------------------------------------*/ typedef struct { vu32 CTRL; vu32 LOAD; vu32 VAL; vuc32 CALIB; } SysTick_TypeDef; /*------------------------ Advanced Control Timer ----------------------------*/ typedef struct { vu16 CR1; u16 RESERVED0; vu16 CR2; u16 RESERVED1; vu16 SMCR; u16 RESERVED2; vu16 DIER; u16 RESERVED3; vu16 SR; u16 RESERVED4; vu16 EGR; u16 RESERVED5; vu16 CCMR1; u16 RESERVED6; vu16 CCMR2; u16 RESERVED7; vu16 CCER; u16 RESERVED8; vu16 CNT; u16 RESERVED9; vu16 PSC; u16 RESERVED10; vu16 ARR; u16 RESERVED11; vu16 RCR; u16 RESERVED12; vu16 CCR1; u16 RESERVED13; vu16 CCR2; u16 RESERVED14; vu16 CCR3; u16 RESERVED15; vu16 CCR4; u16 RESERVED16; vu16 BDTR; u16 RESERVED17; vu16 DCR; u16 RESERVED18; vu16 DMAR; u16 RESERVED19; } TIM1_TypeDef; /*------------------------ General Purpose Timer -----------------------------*/ typedef struct { vu16 CR1; u16 RESERVED0; vu16 CR2; u16 RESERVED1; vu16 SMCR; u16 RESERVED2; vu16 DIER; u16 RESERVED3; vu16 SR; u16 RESERVED4; vu16 EGR; u16 RESERVED5; vu16 CCMR1; u16 RESERVED6; vu16 CCMR2; u16 RESERVED7; vu16 CCER; u16 RESERVED8; vu16 CNT; u16 RESERVED9; vu16 PSC; u16 RESERVED10; vu16 ARR; u16 RESERVED11[3]; vu16 CCR1; u16 RESERVED12; vu16 CCR2; u16 RESERVED13; vu16 CCR3; u16 RESERVED14; vu16 CCR4; u16 RESERVED15[3]; vu16 DCR; u16 RESERVED16; vu16 DMAR; u16 RESERVED17; } TIM_TypeDef; /*----------------- Basic timer TIM6 -----------------------------------------*/ typedef struct { vu16 CR1; u16 RESERVED0; vu16 DIER; u16 RESERVED1; vu16 SR; u16 RESERVED2; vu16 EGR; u16 RESERVED3; vu16 CNT; u16 RESERVED4; vu16 PSC; u16 RESERVED5; vu16 ARR; u16 RESERVED6; } TIM6_TypeDef; /*----------------- Universal Synchronous Asynchronous Receiver Transmitter --*/ typedef struct { vu32 CR1; vu32 CR2; vu16 CR3; u16 RESERVED0; vu16 BRR; u16 RESERVED1; u32 GTPR; vu32 RTOR; vu16 RQR; u16 RESERVED2; vu32 ISR; vu32 ICR; vu8 RDR; u8 RESERVED3[3]; vu8 TDR; u8 RESERVED4[3]; } USART_TypeDef; /*------------------------ Window WATCHDOG -----------------------------------*/ typedef struct { vu32 CR; vu32 CFR; vu32 SR; } WWDG_TypeDef; /******************************************************************************/ /* Peripheral memory map */ /******************************************************************************/ /* Peripheral and SRAM base address in the alias region */ #define PERIPH_BB_BASE ((u32)0x42000000) #define SRAM_BB_BASE ((u32)0x22000000) /* Peripheral and SRAM base address in the bit-band region */ #define SRAM_BASE ((u32)0x20000000) #define PERIPH_BASE ((u32)0x40000000) /* Peripheral memory map */ #define APBPERIPH_BASE PERIPH_BASE #define AHB1PERIPH_BASE (PERIPH_BASE + 0x20000) #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000) #define TIM3_BASE (APBPERIPH_BASE + 0x0400) #define TIM6_BASE (APBPERIPH_BASE + 0x1000) #define TIM14_BASE (APBPERIPH_BASE + 0x2000) #define RTC_BASE (APBPERIPH_BASE + 0x2800) #define WWDG_BASE (APBPERIPH_BASE + 0x2C00) #define IWDG_BASE (APBPERIPH_BASE + 0x3000) #define SPI2_BASE (APBPERIPH_BASE + 0x3800) #define USART2_BASE (APBPERIPH_BASE + 0x4400) #define I2C1_BASE (APBPERIPH_BASE + 0x5400) #define I2C2_BASE (APBPERIPH_BASE + 0x5800) #define PWR_BASE (APBPERIPH_BASE + 0x7000) #define SYSCFG_BASE (APBPERIPH_BASE + 0x10000) #define EXTI_BASE (APBPERIPH_BASE + 0x10400) #define ADC_BASE (APBPERIPH_BASE + 0x12400) #define TIM1_BASE (APBPERIPH_BASE + 0x12C00) #define SPI1_BASE (APBPERIPH_BASE + 0x13000) #define USART1_BASE (APBPERIPH_BASE + 0x13800) #define TIM15_BASE (APBPERIPH_BASE + 0x14000) #define TIM16_BASE (APBPERIPH_BASE + 0x14400) #define TIM17_BASE (APBPERIPH_BASE + 0x14800) #define DMA_BASE (AHB1PERIPH_BASE + 0x0000) #define DMA_Channel1_BASE (AHB1PERIPH_BASE + 0x0008) #define DMA_Channel2_BASE (AHB1PERIPH_BASE + 0x001C) #define DMA_Channel3_BASE (AHB1PERIPH_BASE + 0x0030) #define DMA_Channel4_BASE (AHB1PERIPH_BASE + 0x0044) #define DMA_Channel5_BASE (AHB1PERIPH_BASE + 0x0058) #define RCC_BASE (AHB1PERIPH_BASE + 0x1000) #define FLASH_BASE (AHB1PERIPH_BASE + 0x2000) #define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000) #define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400) #define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800) #define GPIOD_BASE (AHB2PERIPH_BASE + 0x0c00) #define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400) /* System Control Space memory map */ #define SCS_BASE ((u32)0xE000E000) #define SysTick_BASE (SCS_BASE + 0x0010) #define NVIC_BASE (SCS_BASE + 0x0100) #define SCB_BASE (SCS_BASE + 0x0D00) /******************************************************************************/ /* Peripheral declaration */ /******************************************************************************/ #define TIM1 ((TIM1_TypeDef *) TIM1_BASE) #define TIM3 ((TIM_TypeDef *) TIM3_BASE) #define TIM6 ((TIM6_TypeDef *) TIM6_BASE) #define TIM14 ((TIM_TypeDef *) TIM14_BASE) #define TIM15 ((TIM_TypeDef *) TIM15_BASE) #define TIM16 ((TIM_TypeDef *) TIM16_BASE) #define TIM17 ((TIM_TypeDef *) TIM17_BASE) #define RTC ((RTC_TypeDef *) RTC_BASE) #define WWDG ((WWDG_TypeDef *) WWDG_BASE) #define IWDG ((IWDG_TypeDef *) IWDG_BASE) #define USART2 ((USART_TypeDef *) USART2_BASE) #define USART1 ((USART_TypeDef *) USART1_BASE) #define I2C1 ((I2C_TypeDef *) I2C1_BASE) #define I2C2 ((I2C_TypeDef *) I2C2_BASE) #define PWR ((PWR_TypeDef *) PWR_BASE) #define EXTI ((EXTI_TypeDef *) EXTI_BASE) #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) #define ADC1 ((ADC_TypeDef *) ADC1_BASE) #define ADC2 ((ADC_TypeDef *) ADC2_BASE) #define SPI1 ((SPI_TypeDef *) SPI1_BASE) #define SPI2 ((SPI_TypeDef *) SPI2_BASE) #define USART1 ((USART_TypeDef *) USART1_BASE) #define USART2 ((USART_TypeDef *) USART2_BASE) #define DMA ((DMA_TypeDef *) DMA_BASE) #define DMA_Channel1 ((DMA_Channel_TypeDef *) DMA_Channel1_BASE) #define DMA_Channel2 ((DMA_Channel_TypeDef *) DMA_Channel2_BASE) #define DMA_Channel3 ((DMA_Channel_TypeDef *) DMA_Channel3_BASE) #define DMA_Channel4 ((DMA_Channel_TypeDef *) DMA_Channel4_BASE) #define DMA_Channel5 ((DMA_Channel_TypeDef *) DMA_Channel5_BASE) #define DMA_Channel6 ((DMA_Channel_TypeDef *) DMA_Channel6_BASE) #define DMA_Channel7 ((DMA_Channel_TypeDef *) DMA_Channel7_BASE) #define FLASH ((FLASH_TypeDef *) FLASH_BASE) #define OB ((OB_TypeDef *) OB_BASE) #define RCC ((RCC_TypeDef *) RCC_BASE) #define SysTick ((SysTick_TypeDef *) SysTick_BASE) #define NVIC ((NVIC_TypeDef *) NVIC_BASE) #define SCB ((SCB_TypeDef *) SCB_BASE) #define eint() asm volatile("cpsie i") #define dint() asm volatile("cpsid i") #endif // __STM32F030_H typedef unsigned char uint8; typedef unsigned short uint16; typedef unsigned int uint32; typedef unsigned int uint; typedef int bool;